3d3323 monolithic triple fixed delay line (series 3d3323) features packages 1 2 3 4 8 7 6 5 i1 i2 i3 gnd vdd o1 o2 o3 3d 3323z so ic (150 m il) ? all-silicon, low-power cmos technology ? vapor phase, ir and wave solderable ? low ground bounce noise ? leading- and trailing-edge accuracy ? delay range: 10 through 6000ns ? delay tolerance: 2% or 1.0ns ? temperature stability : 3% typ (-40c to 85c) f o r mechanical dimensions, click here . f o r package marking details, click here . ? vdd stability : 1% typic a l (3.0v to 3.6v) ? minimum input pulse w i dth: 20% of total delay pin descriptions i1 delay line 1 input i2 delay line 2 input i3 delay line 3 input o1 delay line 1 output o2 delay line 2 output o3 delay line 3 output vdd +3.3 volts gnd ground n/c no connection functional description the 3d3323 triple delay line product fa mily consists of fixed-delay cmos integrated circuits. each package contains three matched, independent delay lines. delay val ues can range from 10ns through 6000ns. the input is reproduced at the output without inversion, shifted in time as per the us er-specified dash number. the 3d3323 is cmos-compatible and features both rising- and falling-edge accuracy . the all-cmos 3d3323 integrated circuit has been designed as a reliable, economic alternative to hybr id fixed delay lines. it is offered in a space saving surface mount 8-pin soic. table 1: part number specifications dela y i n p u t r e s t r i c t i o n s pa rt number per line (ns) max operating frequency a b solute max oper. freq. min operating pulse w i dth a b solute min oper . p . w . 3d3323z-10 10 1.0 33.3 mhz 100.0 mhz 15.0 ns 5.0 ns 3d3323z -15 15 1.0 22.2 mhz 100.0 mhz 22.5 ns 5.0 ns 3d3323z -20 20 1.0 16.7 mhz 100.0 mhz 30.0 ns 5.0 ns 3d3323z -25 25 1.0 13.3 mhz 83.3 mhz 37.5 ns 6.0 ns 3d3323z -30 30 1.0 11.1 mhz 71.4 mhz 45.0 ns 7.0 ns 3d3323z -40 40 1.0 8.33 mhz 62.5 mhz 60.0 ns 8.0 ns 3d3323z -50 50 1.0 6.67 mhz 50.0 mhz 75.0 ns 10.0 ns 3d3323z -100 100 2.0 3.33 mhz 25.0 mhz 150.0 ns 20.0 ns 3d3323z -200 200 4.0 1.67 mhz 12.5 mhz 300.0 ns 40.0 ns 3d3323z -500 500 10.0 0.67 mhz 5.00 mhz 750.0 ns 100.0 ns 3d3323z -1000 1000 20 0.33 mhz 2.50 mhz 1500.0 ns 200.0 ns 3d3323z -2000 2000 40 0.17 mhz 1.25 mhz 3000.0 ns 400.0 ns 3d3323z -5000 5000 100 0.07 mhz 0.50 mhz 7500.0 ns 1000.0 ns 3d3323z -6000 6000 120 0.05 mhz 0.42 mhz 9000.0 ns 1200.0 ns note: a n y delay betw een 10 and 6000 ns not show n is also av ailable. ? 2007 data delay dev i ces doc #06017 data delay devices, inc. 1 6/25/2007 3 mt. prospect ave. clifton, nj 07013
3d3323 application notes operational description the 3d3323 triple delay line architecture is shown in figure 1. the individual delay lines are composed of a number of delay cells connected in series. each delay line produces at its output a replica of the signal present at its input, shifted in time. the delay lines are matched and share the same compensation signals, which minimizes line-to-line delay deviations over temperature and supply voltage variations. input signal characteristics the frequency and/or pulse width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. the reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. therefore a maximum and an absolute maximum operating input frequency and a minimum and an absolute minimum operating pulse width have been specified. operating frequency the absolute maximum operating frequency specification, tabulated in table 1 , determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. the maximum operating frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed. to guarantee the table 1 delay accuracy for input frequencies higher than the maximum operating frequency , the 3d3323 must be tested at the user operating frequency. therefore, to facilitate production and device identification, the part number w ill include a custom reference designator identifying the intended frequency of operation. the programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. nev e rtheless, it is strongly recommended that the engineering staff at data delay devices be consulted. operating pulse width the absolute minimum operating pulse width (high or low) specification, tabulated in table 1 , determines the smallest pulse width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. the minimum operating pulse width (high or low) specification determines the smallest pulse width of the delay line input signal for which the output delay accuracy tabulated in table 1 is guaranteed. to guarantee the table 1 delay accuracy for input pulse width smaller than the minimum operating pulse width , the 3d3323 must be tested at the user operating pulse width. therefore, to facilitate production and device identification, the part number w ill include a o1 i1 del a y li ne del a y li ne del a y li ne o2 i2 o3 i3 te m p & vd d com pens at i o n vdd gnd figure 1: 3d3323 functional diagram doc #06017 data delay devices, inc. 2 6/25/2007 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3d3323 doc #06017 data delay devices, inc. 3 6/25/2007 3 mt. prospect ave. clifton, nj 07013 application notes (cont?d) custom reference designator identifying the intended frequency and duty cycle of operation. the programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy , if at all. nev e rtheless, it is strongly recommended that the engineering staff at data delay devices be consulted. power supply and temperature considerations the delay of cmos integrated circuits is strongly dependent on power supply and temperature. the monolithic 3d3323 programmable delay line utilizes novel and innovative compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature. the thermal coefficient is reduced to 300 ppm/c , which is equivalent to a variation , over the -40c to 85c operating range, of 3% from the room-temperature delay settings and/or 1.0ns , whichever is greater. the pow er supply coefficient is reduced, over the 3.0v to 3.6v operating range, to 1% of the delay settings at the nominal 3.3vdc power supply and/or 2.0ns , whichever is greater. it is essential that the pow er supply pin be adequately by passed and filtered. in addition, the pow er bus should be of as low an impedance construction as possible. pow e r planes are preferred. device specifications table 2: absolute maximum ratings p a r a m e t e r s y m b o l m i n m a x u n i t s n o t e s dc supply voltage v dd - 0 . 3 7 . 0 v input pin voltage v in - 0 . 3 v dd +0. 3 v input pin current i in - 1 . 0 1 . 0 m a 2 5 c storage temperature t st rg - 5 5 1 5 0 c lead temperature t lead 3 0 0 c 1 0 s e c table 3: dc electrical characteristics (-40c to 85c, 3.0v to 3.6v) p a r a m e t e r s y m b o l m i n m a x u n i t s n o t e s static supply current* i dd 5 m a high level input voltage v ih 2 . 0 v low level input voltage v il 0 . 8 v high level input current i ih - 1 1 a v ih = v dd low level input current i il - 1 1 a v il = 0v high level output current i oh - 4 . 0 m a v dd = 4.75v v oh = 2.4v low level output current i ol 4 . 0 m a v dd = 4.75v v ol = 0.4v output rise & fall time t r & t f 2 n s c ld = 5 pf *i dd (dy namic) = 3 * c ld * v dd * f input capacitance = 10 pf ty pical w here: c ld = average capacitance load/line (pf) output load capacitance (c ld ) = 25 pf max f = input frequency (ghz)
3d3323 silicon delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c r load : 10k ? 10% supply voltage (vcc): 3.3v 0.1v c load : 5pf 10% input pulse: high = 3.0v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 ? max. 10k ? 470 ? 5pf dev i c e under te s t di gi t a l s c ope rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) pulse width: pw in = 1.25 x total delay period: per in = 2.5 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. out 1 out 2 out 3 out tr i g in re f tr i g f i g u r e 2: t est s e t u p de v i ce unde r t est (d u t ) d i g i t a l sc o pe/ t i m e i n t e rv a l count e r pu l s e ge ne ra t o r com p ut e r sy st em pr in t e r in 3 in 2 in 1 figur e 3 : t i m i ng d i a g r a m t pl h t ph l per in pw in t ris e t fa l l 0. 6v 0. 6v 1. 5v 1. 5v 2. 4v 2. 4v 1. 5v 1. 5v v ih v il v oh v ol in p u t s ign a l ou tp u t s ign a l doc #06017 data delay devices, inc. 4 6/25/2007 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
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